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fedl7029-04 issue date: jun. 8, 2007 ML7029 multifunction adpcm codec 1/29 general description the ML7029 is a single channel ad pcm codec ic which performs mutual transcoding between the analog voice band signal and 32 kbps adpcm serial data. features ? single 3 v power supply operation (v dd : 2.7 to 3.6 v) ? adpcm algorithm: itu-t g.726 (32 kbps, 24 kbps, 16 kbps) ? full-duplex transmit/receive operation ? transmit/receive synchronous mode only ? pcm data format: ? -law ? serial pcm/adpcm transmission data rate: 64 kbps to 2048 kbps (when sync = 8 khz) ? low power consumption operating mode: 18 mw typ. (v dd = 3.0 v, sync = 8 khz) power-down mode: 0.03 mw typ. (v dd = 3.0 v, sync = 8 khz) ? sampling frequency: 6 khz to 21 khz selectable (however, there are limitations to 16 khz or higher frequencies) ? master clock frequency: sampling frequency ? 1296 when sync = 8 khz: 10.368 mhz ? transmit/receive mute, transmit/r eceive programmable gain control ? side tone path with programmable attenuation (8-step level adjustment) ? serial mcu interface control ? package: 30-pin plastic ssop (ssop30-p-56-0.65-k) (ML7029)
fedl7029-04 ML7029 2/29 block diagram lpf pcm expander a/d conv. bpf/ lpf pcm compander pcmso pcmri ain? gsx d/a conv. vfro vref sg mcu i/f v a v d dg ag mck pdn dout din den exck bclk sync 20 k ? 20 k ? cr2-b6 to b4 cr2-b2 to b0 cr3-b7 to b5 adpcm pcmsi is ir pcmro cr2-b7 txon/ off cr2-b3 rxon/ off
fedl7029-04 ML7029 3/29 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 gsx ain? sg v a ag vfro dg pdn v d bclk sync pcmso pcmsi is ir pcmro pcmri mck den exck din dout nc nc nc nc nc nc nc nc nc: no connection 30-pin plastic ssop
fedl7029-04 ML7029 4/29 pin functional descriptions ain?, gex transmit analog input and transmit level adjustment. ain? is connected to the inverting input of the transmit amplifier. gsx is connected to the transmit amplifier output. during power-down mode, the gsx output is a high impedance state. vfro receive analog output. during powe r-down mode, the vfro output is in a high impedance state. sg analog signal ground. the output voltage of this pin is approximately 1.4 v. put 10 ? f plus 0.1 ? f (ceramic type) bypass capacitors between this pin and ag. during power-down, this output voltage is 0 v. this pin should be used via a buffer if used externally. ag analog ground. dg digital ground. this ground is separated from the analog signal ground pin (ag). the dg pin must be kept as close as possible to ag on the pcb. va analog +3 v power supply. v d digital +3 v power supply. this power supply is separated from the analog signal power supply pin (v a ). the v d pin must be kept as close as possible to v a on the pcb. pdn power-down and reset control input. a ?0? level makes the ic enter a power-down state. at the same time, all control regist er data are reset to the initial state. set this pin to ?1? during normal operati ng mode. the power-down state is controlled by a logical or with cr0-b5 of the cont rol register. when using pdn for power-down and reset control, set cr0-b5 to digital ?0?. the reset width (a ?l? level period) should be 200 ns or more. be sure to reset the control registers by executing this power down to keep this pin to digital ?0?level for 200 ns or longer after the power is turned on and v dd exceeds 2.7 v.
fedl7029-04 ML7029 5/29 mck master clock input. the frequency is 1296 times the sync signal. for example, it is 10.368 mhz when the sync signal is 8 khz. the master clock signal may be asynchronous with bclk and sync. pcmso transmit pcm data output. pcm is output from msb in synchronization with the rising edge of bclk and xsync. refer to figure 1. during power-down, the pcmso output is at ?l? level. pcmsi transmit pcm data input. this signal is converted to the transmit adpcm data, pc m is shifted in synchronization with the falling edge of bclk. normally, this pin is connected to pcmso. refer to figure 1. pcmro receive pcm data output. pcm is the output signal after adpcm decoder processing. this signal is output serially from msb in synchronization with the rising edge of bclk and rsync. refer to figure 1. during power-down, the pcmro output is at ?l? level. pcmri receive pcm data input. pcm is shifted on the rising edge of the bclk and input from msb. normally, this pi n is connected to pcmro. refer to figure 1. is transmit adpcm signal output. after having encoded pcm with adpcm, the signal is output from msb in synchronization with the rising edge of bclk and xsync. refer to figure 1. this pin is at ?h? level during power-down. ir receive adpcm signal input. this input signal is shifted serially on the falling edge of bclk and sync and input from msb. refer to figure 1. bclk shift clock input for the pcm and adpcm data. the frequency is set in the range of 8 to 256 times the sync frequency. refer to figure 1.
fedl7029-04 ML7029 6/29 symc sampling input for the pcm and adpcm data. the frequency is 8 khz or 11.025 khz and is selected by the control register data cr3-b1. synchronize this signal with bclk signal. sync is used to indicate the msb of the pcm data stream. refer to figure 1. figure 1 pcm and adpcm interface basic timing 125 ? s (sync = 8 khz) bclk sync msb lsb pcmso/pcmsi/ pcmro/pcmri msb lsb is/ir
fedl7029-04 ML7029 7/29 den, exck, din, dout serial control ports for mcu interface. reading and writing data are performed by an external mcu through these pins. the 8-byte cotrol registers (cr0 to 7) are provided on the device. den is the ?enable? control signal input, exck is the data shift clock input, din is the address and data input, and dout is the data output. figures 2-1 and 2-2 show the input/output timing diagram. during power-down, the dout output is in a high impedance state. figure 2-1 mcu interface input/output timing (din = 12 bits) (a) data write timing diagram (b) data read timing diagram exck a2 a1 a0 w b7 b6 b5 b4 b3 b2 b1 b0 den din dout high impedance exck den a2 a1 a0 r din b7 b6 b5 b4 b3 b2 b1 b0 dout high impedance exck den din exck den din figure 2-2 mcu interface input/output timing (din = 16 bits) dout dout b7 b6 b5 b4 b3 b2 b1 b0 (a) data write timing diagram high impedance a2 a1 a0 w (b) data read timing diagram a2 a1 a0 r b7 b6 b5 b4 b3 b2 b1 b0 high impedance
fedl7029-04 ML7029 8/29 table 1 shows the register map. table 1 control register map address control and detect data name a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr0 0 0 0 ? ? pdn all ? ? ? ? ? r/w cr1 0 0 1 mode 1 mode 0 tx reset rx reset tx mute rx mute ? rx pad r/w cr2 0 1 0 tx on/off tx gain2 tx gain1 tx gain0 rx on/off rx gain2 rx gain1 rx gain0 r/w cr3 0 1 1 side tone gain2 side tone gain1 side tone gain0 ? ? ? hpf 8k/11k hpf on/off r/w r/w : read/write enable
fedl7029-04 ML7029 9/29 absolute maximum ratings parameter symbol condition rating unit power supply voltage v dd ? ?.3 to +5.0 v analog input voltage v ain ? ?0.3 to v dd +0.3 v digital input voltage v din ? ?0.3 to v dd +0.3 v storage temperature t stg ? ?55 to +150 ? c recommended operation conditions parameter symbol conditio n min. typ. max. unit power supply voltage v dd voltage must be fixed +2.7 3.0 +3.6 v operating temperature range ta ? ?25 +25 +70 ? c digital input high voltage v ih digital input pins 0.45 ?? v dd ? v dd v digital input low voltage v il digital input pins 0 ? 0.16 ?? v dd v master clock frequency f mck1 mck 7.776 10.368 20.736 mhz master clock frequency accuracy f mck2 mck ?0.01% sync ??? 1296 +0.01% mhz bit clock duty f bck bclk sync ?? 8? sync ?? 256 khz sampling frequency (*1) f sync sync 6.0 8.0 16 khz master clock duty ratio d mck mck ? ( ? 20.736 mhz) 30 50 70 % clock duty ratio d clk bclk, exck 30 50 70 % digital input rise time t ir digital input pins ? ? 50 ns digital input fall time t if digital input pins ? ? 50 ns pcm sync signal setting time (continuous bclk) t bs bclk ??? sync (see fig. 3-1) 100 ? ? ns pcm sync signal setting time (burst mode clock) t sb bclk ?? sync (see fig. 3-2) 0 ? 20 ? s sync signal width (continuous bclk) t ws sync (see fig. 3-1) 1bclk ? sync ?1 bclk ? s sync signal width (burst mode clock) t wsb sync (see fig. 3-2) 1bclk ? burst clock ?1 ? s pcm, adpcm setup time t ds ? 100 ? ? ns pcm, adpcm hold time t dh ? 100 ? ? ns digital output load c dl digital output pins ? ? 100 pf bypass capacitors for sg c sg sg to ag 10+0.1 ? ? ? f *1: refer to the appendix.
fedl7029-04 ML7029 10/29 electrical characteristics dc characteristics (v dd = 2.7 to 3.6 v, ta = ?25 to +70 ? c) parameter symbol conditio n min. typ. max. unit power supply current i dd1 operating mode no signal ? 6.0 12 ma (v dd = 3.0 v, sync = 8 khz) i dd2 power down mode (input pins are fixed) ? 0.01 0.1 ma input leakage current i ih v i = v dd ? ? 2.0 a i il v i = 0 v ? ? 0.5 a output high voltage v oh i oh = 4 ma 2.4 ? ? v output low voltage v ol i ol = ?4 ma ? ? 0.4 v input capacitance c in ? ? 5 ? pf analog interface characteristics (v dd = 2.7 to 3.6 v, ta = ?25 to +70 ? c) parameter symbol conditio n min. typ. max. unit input resistance r in ain? ? 10 ? m ? output load resistance r l gsx, vfro 20 ? ? k ? output load capacitance c l gsx, vfro ? ? 100 pf output amplitude (*2) v o1 gsx, vfro (r l = 20 k ? ) ? ? 1.3 v pp offset voltage v of gsx, vfro ?100 ? +100 mv sg output voltage v sg sg ? 1.4 ? v sg output resistance r sg sg ? 40 ? k ? sg warm-up time t sg sg ? ag 10+0.1 ? f (rise time to max. 90% level) ? 700 ? ms *2: ?7.7 dbm (600 ? ) = 0 dbm0, +3.17 dbm0 = 1.3 v pp
fedl7029-04 ML7029 11/29 ac characteristics (v dd = 2.7 to 3.6 v, ta = ?25 to +70 ? c) condition parameter symbol freg. (hz) level (dbm0) min. typ. max. unit lb8t1 60 30 ? ? db lb8t2 300 ?0.5 ? 1.5 db lb8t3 1015 reference db lb8t4 3400 ?0.5 ? 1.0 db transmit frequency response sync = 8 khz bpf lb8t5 3970 0 12 ? ? db lb11t1 60 30 ? ? db lb11t2 300 ?0.5 ? 1.5 db lb11t3 1400 reference db lb11t4 4690 ?0.5 ? 1.0 db transmit frequency response sync = 11.025 khz bpf lb11t5 5470 0 12 ? ? db ll8t1 300 ?0.5 ? 0.5 db ll8t2 1015 reference db ll8t3 3400 ?0.5 ? 1.0 db transmit frequency response sync = 8 khz lpf ll8t4 3970 0 12 ? ? db ll11t1 300 ?0.5 ? 0.5 db ll11t2 1400 reference db ll11t3 4690 ?0.5 ? 1.0 db transmit frequency response sync = 11.025 khz lpf ll11t4 5470 0 12 ? ? db ll8r1 300 ?0.5 ? 0.5 db ll8r2 1015 reference db ll8r3 3400 ?0.5 ? 1.0 db receive frequency response sync = 8 khz lpf ll8r4 3970 0 12 ? ? db ll11r1 300 ?0.5 ? 0.5 db ll11r2 1400 reference db ll11r3 4690 ?0.5 ? 1.0 db receive frequency response sync = 11.025 khz lpf ll11r4 5470 0 12 ? ? db sd8t1 3 35 ? ? db transmit s/n ratio sync = 8 khz (*3) sd8t2 f = 1015 hz ?40 28 ? ? db sd8r1 3 35 ? ? db receive s/n ratio sync = 8 khz (*3) sd8r2 f = 1015 hz ?40 28 ? ? db sd16t1 3 35 ? ? db transmit s/n ratio sync = 16 khz (*3) sd16t2 f = 1015 hz ?40 28 ? ? db sd16r1 3 35 ? ? db receive s/n ratio sync = 16 khz (*3) sd16r2 f = 1015 hz ?40 28 ? ? db n idlt ain? = sg ? ? ?68 dbm0pp idle channel noise sync = 8 khz (*3) n idlr ? (*4) ? ? ?72 dbm0pp n idlt ain? = sg ? ? ?68 dbm0pp idle channel noise sync = 16 khz (*3) n idlr ? (*4) ? ? ?72 dbm0pp a vt 1015 hz(gsx) sync = 8 khz 0 0.285 0.320 0.359 vrms absolute signal amplitude (*5) a vr 1015 hz(vfro) sync = 8 kh z 0 0.285 0.320 0.359 vrms *3: use the p-message weighted filter *4: pcmri input code ?11111111? (-law) *5: 0.320 vrms = 0 dbm0 = ?7.7 dbm (600 ? )
fedl7029-04 ML7029 12/29 digital interface (v dd = 2.7 to 3.6 v, ta = ?20 to +70 ? c) parameter symbol condition reference min. typ. max. unit t sdx , t sdr 0 ? 200 ns t xd1 , t rd1 0 ? 200 ns t xd2 , t rd2 0 ? 200 ns digital input/output setting time t xd3 , t rd3 1lsttl+100 pf fig. 3-1 fig. 3-2 0 ? 200 ns t 1 50 ? ? ns t 2 50 ? ? ns t 3 50 ? ? ns t 4 50 ? ? ns t 5 100 ? ? ns t 6 30 ? ? ns t 7 30 ? ? ns t 8 0 ? 50 ns t 9 20 ? ? ns t 10 20 ? ? ns t 11 0 ? 50 ns ? ? 3.5(*6) serial port digit al input/output setting time t 12 c l = 50 pf fig. 4-1 fig. 4-2 5.0(*6) ? ? ns shift clock frequency f exck exck exck ? ? 10 mhz *6: don?t raise the den in the range (3.5ns to 5.0ns) delayed from falling edge of the 12 th exck. ac characteristics (programmable gain stages) (v dd = 2.7 to 3.6 v, ta = -25 to +70 ? c) parameter symbol conditio n min. typ. max. unit gain accuracy d g all stages, to programmed value sync = 8 khz ?1 0 +1 db
fedl7029-04 ML7029 13/29 timing diagram transmit side pcm/ad pcm data interface receive side pcm/ad pcm data interface figure 3-1 pcm/adpcm data interface (continuous bclk) t xd3 t ws t bs t bs bclk sync msb t sdx t xd1 t xd2 pcmso lsb msb t sdx is lsb t xd3 t rd3 t ws t bs t bs bclk sync msb t sdr t rd1 t rd2 pcmro lsb msb t ds ir t dh lsb t rd3
fedl7029-04 ML7029 14/29 transmit side pcm/ad pcm data interface receive side pcm/ad pcm data interface figure 3-2 pcm/adpcm data interface (burst mode clock) t xd3 t wsb t sb bclk sync msb t xd1 t xd2 pcmso lsb msb is lsb t xd3 t rd3 t wsb t sb bclk sync msb t rd1 t rd2 pcmro lsb msb t ds ir t dh lsb t rd3
fedl7029-04 ML7029 15/29 serial port data tran sfer for mcu interface figure 4-1 serial control port interface (din = 12 bits) figure 4-2 serial control port interface (din = 16 bits) 1 2 3 4 5 6 15 16 w/r a 2 a 1 a 0 b7 b6 0 b7 b6 den exck din dout t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 14 13 12 b0 0 b0 1 2 3 4 5 611 12 w/r a 2 a 1 a 0 b7 b6 b1 b0 b7 b6 b1 b0 den exck din dout t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 11 t 10 t 12
fedl7029-04 ML7029 16/29 functional description control registers (1) cr0 (basic operating mode setting) b7 b6 b5 b4 b3 b2 b1 b0 cr0 ? ? pdn all ? ? ? ? ? initial value * * 0 * * * * * note: initial value: reset state by pdn (*: don?t care) b7, b6, b4 to b0 : not used (these pins are used to test the device. they should be set to ?0? during normal operation.) b5 : power-down (entire system); 0/power-on, 1/power-down 0 red with the inverted external power-down signals. when using this data, set the rdn pin to ?1?. (2) cr1 (adpcm operating mode setting) b7 b6 b5 b4 b3 b2 b1 b0 cr1 mode1 mode0 tx reset rx reset tx mute rx mute ? rx pad initial value 0 0 0 0 0 0 * 0 b7, b6: adpcm data compression algorithm select (output bit select); (0, 0): 4-bit output (32 kbps) (0, 1): 8-bit output (64 kbps) (1, 0): 3-bit output (24 kbps) (1, 1): 2-bit output (16 kbps) data rates in parentheses: when sync = 8 khz b5 : adpcm of transmit reset (specified by g.726); 1/reset* b4 : adpcm of receive reset (specified by g.726); 1/ reset* b3 : adpcm transmit data mute; 1/mute b2 : adpcm receive data mute; 1/mute b1 : not used (this pin is used to test the device. it should be set to ?0? during normal operation. b0 : receive side pad; 1/inserted in th e receive side voice path, 12 db loss 0/no pad * the reset width should be 1/ f sample ? s or more. the transmit and receive sides cannnot be reset separately. they must be reset at the same time.
fedl7029-04 ML7029 17/29 (3) cr2 (pcm codec operating mode setting and transmit/receive gain adjustment) b7 b6 b5 b4 b3 b2 b1 b0 cr2 tx on/off tx gain2 tx gain1 tx gain0 rx on/off rx gain2 rx gain1 rx gain0 initial value 0 0 1 1 0 0 1 1 b7 : transmit pcm signal on/off; 0/on, 1/off b6, b5, b4 : transmit signal gain adjustment, refer to table 2. b3 : receive pcm signal on/off; 0/on, 1/off b2, b1, b0 : receive signal gain adju stment, refer to table 2. table 2 transmit/receive gain setting (when sync = 8 khz) b6 b5 b4 transmit gain b2 b1 b0 receive gain 0 0 0 ?6 db 0 0 0 ?6 db 0 0 1 ?4 db 0 0 1 ?4 db 0 1 0 ?2 db 0 1 0 ?2 db 0 1 1 0 db 0 1 1 0 db 1 0 0 +2 db 1 0 0 +2 db 1 0 1 +4 db 1 0 1 +4 db 1 1 0 +6 db 1 1 0 +6 db 1 1 1 +8 db 1 1 1 +8 db
fedl7029-04 ML7029 18/29 (4) cr3 (side tone gain setting) b7 b6 b5 b4 b3 b2 b1 b0 cr3 side tone gain2 side tone gain1 side tone gain0 ? ? ? hpf 8k/11k hpf on/off initial value 0 0 0 * * * 0 0 b7, b6, b5 : side tone path gain setting. refer to table 3. b4 to b2 : not used (these pins are used to test the device. they should be set to ?0? during normal operation.) table 3 side tone pash gain setting (when sync = 8 khz) b7 b6 b5 side tone path gain 0 0 0 off 0 0 1 ?21 db 0 1 0 ?19 db 0 1 1 ?17 db 1 0 0 ?15 db 1 0 1 ?13 db 1 1 0 ?11 db 1 1 1 ?9 db b1: transmit hpf cut-off frequency select; 0/the cut-off frequency of the transmit hpf is the sampling frequency ? 0.0275. when sync = 8 khz: 220 hz, when sync = 11.025 khz: 300 hz. the transmit frequency characteristics are not gu aranteed when selecting sync = 11.025 khz. 1/the cut-off frequency of the transmit hpf is the sampling frequency ? 0.0200. when sync = 8 khz: 160 hz, when sync = 11.025 khz: 220 hz. the transmit frequency characteristics are not guaranteed when selecting sync = 8 khz. b0: transmit hpf on/off; 0/on, 1/off for the frequency characteristics, refer to figures 9 to 12 in the reference data.
fedl7029-04 ML7029 19/29 application circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 gsx nc ain? nc sg nc v a nc ag nc vfro nc nc dg pdn v d bclk sync pcmso pcmsi is ir pcmro pcmri nc mck den exck din dout master clock mcu i/f pcm i/f power-down r1 0.1 f 10 f r2 ML7029 adpcm data 10 f v dd
fedl7029-04 ML7029 20/29 application information burst mode clock this device can be operated by a burst mode clock (see below). figure 5 example of burst mode clock relationship between sync and blck b figure 7 sync bclk 1 2 3 4 5 6 7 8 ir (2) a dpcm data input 0.52/f sample ? s receive side tr 1 ? s (range of data slip occurrence) 1/f sample ? s a figure 6 sync bclk 1 2 3 4 5 6 7 8 pcmsi (1) pcm data input 0.83/f sample ? s 1 ? s (range of data slip occurrence) transmit side ts 1/f sample ? s bclk sync sync signal pulse width : min. 1-bit clock : max. ( number of clocks in burst mode ) ? 1 1 2 3 4 5 6 7 8 1/f sample ? s
fedl7029-04 ML7029 21/29 (1): pcm data serial to parallel conversion output (2): adpcm data serial to parallel conversion output a: (1) data internal latch timing b: (2) data internal latch timing figure 8 in this device, internal operating timing is generated accord ing to the sync signal (see figure 8). therefore, a data slip may occur in the following timing when the pcm and adpcm data is input. 1. when the pcm signal (pcmsi) is captured if ts: pcm signal output (1) after serial/parallel conversion and a: internal latch timing in figure 6 overlap, a data slip occurs. 2. when the adpcm signal (ir) is captured if tr: adpcm signal output (2) after serial/parallel conv ersion and b: internal latch timing in figure 7 overlap, a data slip occurs. the data slip occurs at the timing of 1 and 2 above. ther efore, taking internal clock jitters and ic internal delay into consideration, the timing of sync and bclk signals should not be set up in the range of about 1 ? s from the timing a and b. pcmsi is internal clock generation adpcm cod s/p a sync bclk (1) pcmro ir adpcm dec p/s latch b (2) latch s/p p/s latch latch
fedl7029-04 ML7029 22/29 reference data transmit frequency characteristics figure 9 transmit bandpass filter characteristic (fs = 8 khz, cr3-b1, b0 = (0, 0)) figure 10 transmit lowpass filter characteristic (fs = 8 khz, cr3-b1, b0 = (0, 1)) fs = 8 khz transmit bpf characteristic -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 frequency (hz) gain (db) fs = 8khz transmit lpf characteristic -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 frequency (hz) gain (db)
fedl7029-04 ML7029 23/29 figure 11 transmit bandpass filter characteristic (fs = 11.025 khz, cr3-b1, b0 = (1, 0)) figure 12 transmit lowpass filter characteristic (fs = 11.025 khz, cr3-b1, b0 = (1, 1)) fs = 11.025 khz transmit bpf characteristic -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 frequency (hz) gain (db) fs = 11.025 khz transmit lpf characteristic -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 frequency (hz) gain (db) 10000 10000
fedl7029-04 ML7029 24/29 receive frequency characteristics figure 13 receive lowpass filter characteristic (fs = 8 khz, cr3-b1, b0 = (0, *)) fs = 8 khz receive lpf characteristic -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 frequency (hz) gain (db) figure 14 receive lowpass filter characteristic (fs = 11.025 khz, cr3-b1, b0 = (1, *)) fs = 11.025 khz receive lpf characteristic -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 frequency (hz) gain (db) 10000
fedl7029-04 ML7029 25/29 appendix when the sampling frequency is 16 khz or higher: this device enables the operation at 16 khz or higher sampling frequencies under conditions below. however, be aware that the ac characteristics ar e not guaranteed under these conditions. operating conditions at sampling frequency = 19 khz parameter symbol condition min. typ. max. unit power supply voltage v dd voltage must be fixed 3.0 ? 3.6 v operating temperature range ta ? ?25 ? +50 ? c digital input high voltage v ih digital input pin 0.95 ? v dd ? v dd v digital input low voltage v il digital input pin 0 0.05 ? v dd v master clock frequency f mck1 mck ? 24.624 ? mhz master clock frequency accuracy f mck2 mck ?0.01% sync ? 1296 +0.01 mhz sampling frequency f sync sync ? 19 ? khz master clock duty ratio d mck ? 40 ? 70 % transmit s/n ratio (at 3 dbm0 input) sd19t1 ? ? 46.2 ? db transmit s/n ratio (at ?40 dbm0 input) sd19t2 ? ? 24.8 ? db receive s/n ratio (at 3 dbm0 input) sd19r1 ? ? 45.4 ? db receive s/n ratio (at ?40 dbm0 input) sd19r2 ? ? 38.0 ? db
fedl7029-04 ML7029 26/29 operating conditions at sampling frequency = 21 khz parameter symbol condition min. typ. max. unit power supply voltage v dd voltage must be fixed 3.3 ? 3.6 v operating temperature range ta ? ?25 ? +50 ? c digital input high voltage v ih digital input pin 0.95 ? v dd ? v dd v digital input low voltage v il digital input pin 0 0.05 ? v dd v master clock frequency f mck1 mck ? 27.216 ? mhz master clock frequency accuracy f mck2 mck ?0.01% sync ? 1296 +0.01 mhz sampling frequency f sync sync ? 21 ? khz master clock duty ratio d mck ? 40 ? 70 % transmit s/n ratio (at 3 dbm0 input) sd19t1 ? ? 46.1 ? db transmit s/n ratio (at ?40 dbm0 input) sd19t2 ? ? 20.2 ? db receive s/n ratio (at 3 dbm0 input) sd19r1 ? ? 44.8 ? db receive s/n ratio (at ?40 dbm0 input) sd19r2 ? ? 37.8 ? db
fedl7029-04 ML7029 27/29 package dimensions notes for mounting the surface mount type package the surface mount type packages ar e very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform refl ow mounting, contact rohm?s responsible sales person for the product name, package name, pin number, package co de and desired mounting conditions (reflow method, temperature and times). ssop30-p-56-0.65-k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5 m) package weight (g) 0.19 typ. 5 rev. no./last revised 5/dec. 5, 1996 ( unit: mm )
fedl7029-04 ML7029 28/29 revision history page document no. date previous edition current edition description fedl7029-02 nov. 2001 ? ? final edition 2 ? ? final edition 3 fedl7029-03 feb.18, 2004 9 9 changed ?symbol? of setup time and hold time for pcm/ adpcm. 12 12 added t 12 corrected values of serial port digital input/output setting time fedl7029-04 jun. 8, 2007 15 15 added t 12 corrected figure 4-1 serial control port interface
fedl7029-04 ML7029 29/29 notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants an d any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the info rmation specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or othe r rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatso ever for any dispute arising from the use of such technical information. the products specified in this documen t are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe desi gns. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a me dical instrument, transpor tation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety devi ce). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, pleas e contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2011 lapis semiconductor co., ltd.

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